Numbering system
Karnaugh maps
Timing diagrams
Pipelining
Flipflop
Latch
Various types of FF’s, Latch’s
Various Counters (with practical applications)
FIFO
Data transfer synchronisation between components
Race condition
Meta stability
Multiplexer, Using MUX to create various gates, FF
Decoder, encoder, priority decoder
Parity generation
Half adder, full adder
Truth table for HA, FA, Mux, counters
Buffer, inverter
PLL, VCO, clock generation

Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
Clock domain crossing
Reset
Power management in SOC
State machines
Register